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MC10E167 MUX Register

MC10E167 MUX Register Series Datasheet

The ON SEMICONDUCTOR MC10E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW. The 100 Series contains temperature compensation.

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MC10E167FN MC10E167FNG MC10E167FNR2

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