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MC10E156 Mux-Latch

MC10E156 Mux-Latch Series Datasheet

The ON SEMICONDUCTOR MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.


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MC10E156FN MC10E156FNG MC10E156FNR2 MC10E156FNR2G

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