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MC100E154 Mux-Latch

MC100E154 Mux-Latch Series Datasheet

The ON SEMICONDUCTOR MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. The 100 Series contains temperature compensation.

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MC100E154 MC100E154FN

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