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EP910I Classic EPLD

EP910I Classic EPLD Series Datasheet

ALTERA EP910 devices can implement up to 450 usable gates of SSI and MSI logic functions. EP910 devices have 24 macrocells, 12 dedicated input pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 and CLK2 signals are the dedicated clock inputs for the registers in macrocells 13 through 24 and 1 through 12, respectively.


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EP910IDC-15 EP910IDC-25 EP910IDI-15 EP910ILC-12
EP910ILC-15 EP910ILC-25 EP910ILI-12 EP910ILI-15
EP910ILI-25 EP910IPC-15 EP910IPC-25 EP910IPC-35
EP910I Classic EPLD Package Types
family combined
Ceramic Dual Inline Package (CDIP)
family combined
Plastic Dual-In-Line Package (PDIP)
family combined
Plastic Quad J-leaded Chip Carrier (PQCC)
EP910I Classic EPLD Series Part Photos
EP910IDC-15 photos
EP910IDC-15 (4)
EP910ILC-15 photos
EP910ILC-15 (1)
EP910IPC-25 photos
EP910IPC-25 (5)

EP910I Classic EPLD


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EP910I Classic EPLD Part Photos
EP910IDC-15 photos
EP910IDC-15
EP910IDC-15 photos
EP910IDC-15
EP910IDC-15 photos
EP910IDC-15
EP910IDC-15 photos
EP910IDC-15
EP910ILC-15 photos
EP910ILC-15
EP910IPC-25 photos
EP910IPC-25
EP910IPC-25 photos
EP910IPC-25
EP910IPC-25 photos
EP910IPC-25
EP910IPC-25 photos
EP910IPC-25
EP910IPC-25 photos
EP910IPC-25

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