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EP910 Classic EPLD

EP910 Classic EPLD Series Datasheet

ALTERA EP910 devices can implement up to 450 usable gates of SSI and MSI logic functions. EP910 devices have 24 macrocells, 12 dedicated input pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 and CLK2 signals are the dedicated clock inputs for the registers in macrocells 13 through 24 and 1 through 12, respectively.


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EP910ADC-25 EP910AJC-25 EP910ALC-25 EP910APC-25
EP910DC-30 EP910DC-35 EP910DC-40 EP910DI-30
EP910DI-35 EP910DI-40 EP910DM-40 EP910JC-30
EP910JC-35 EP910JC-40 EP910JI-35 EP910JI-40
EP910JM-40 EP910LC-30 EP910LC-30T EP910LC-35
EP910LC-40 EP910LI-30 EP910LI-35 EP910LI-40
EP910PC-30 EP910PC-30T EP910PC-35 EP910PC40
EP910PI-30 EP910PI-35
EP910 Classic EPLD Package Types
family combined
Ceramic Dual Inline Package (CDIP)
family combined
Plastic Dual-In-Line Package (PDIP)
family combined
Plastic Leaded Chip Carrier (PLCC)
family combined
Plastic Quad J-leaded Chip Carrier (PQCC)
EP910 Classic EPLD Series Part Photos
EP910DC-40 photos
EP910DC-40 (4)
EP910LC-30T photos
EP910LC-30T (2)
EP910LC-35 photos
EP910LC-35 (2)
EP910LI-40 photos
EP910LI-40 (5)
EP910PC-35 photos
EP910PC-35 (2)
EP910PC40 photos
EP910PC40 (2)

EP910 Classic EPLD


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EP910 Classic EPLD Part Photos
EP910DC-40 photos
EP910DC-40
EP910DC-40 photos
EP910DC-40
EP910DC-40 photos
EP910DC-40
EP910DC-40 photos
EP910DC-40
EP910LC-30T photos
EP910LC-30T
EP910LC-30T photos
EP910LC-30T
EP910LC-35 photos
EP910LC-35
EP910LC-35 photos
EP910LC-35
EP910LI-40 photos
EP910LI-40
EP910LI-40 photos
EP910LI-40
EP910LI-40 photos
EP910LI-40
EP910LI-40 photos
EP910LI-40
EP910LI-40 photos
EP910LI-40
EP910PC-35 photos
EP910PC-35
EP910PC-35 photos
EP910PC-35
EP910PC40 photos
EP910PC40
EP910PC40 photos
EP910PC40

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