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EP610D Classic EPLD

EP610D Classic EPLD Series Datasheet

ALTERA EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins, and 2 global clock pins (see Figure 8). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 signal is a dedicated global clock input for the registers in macrocells 9 through 16. The CLK2 signal is a dedicated global clock input for registers in macrocells 1 through 8.


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EP610DC-15 EP610DC-20 EP610DC-25 EP610DC-25ES
EP610DC-30 EP610DC35 EP610DI-30 EP610DI-35
EP610DM-10 EP610DM-35
EP610D Classic EPLD Package Types
family combined
Ceramic Dual Inline Package (CDIP)
EP610D Classic EPLD Series Part Photos
EP610DC35 photos
EP610DC35 (6)

EP610D Classic EPLD


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EP610D Classic EPLD Part Photos
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EP610DC35
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EP610DC35
EP610DC35 photos
EP610DC35
EP610DC35 photos
EP610DC35
EP610DC35 photos
EP610DC35
EP610DC35 photos
EP610DC35

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