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CD54HC259 8-Bit Addressable Latch

CD54HC259 8-Bit Addressable Latch Series Datasheet

The TEXAS INSTRUMENTS (TI) ’HC259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky. This latches three active modes and one reset mode. When both the Latch Enable (LE) and Master Reset (MR) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR and LE are high (Memory Mode), all outputs are isolated from the Data input, i.e., all latches hold the last data presented before the LE transition from low to high. A condition of LE low and MR high (Addressable Latch mode) allows the addressed latch’s output to follow the data input; all other latches are unaffected. The Reset mode (all outputs low) results when LE is high and MR is low.

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54HC259/BEAJC 54HC259F 5962-01-279-8253 5962-01-424-3335
5962013424106 85519012A 8551901EA 8551901EX
CD54HC259F CD54HC259F3A HC259 HC259A
HC259M HC259N JM38510/65402B2A JM38510/65402BEA
JM38510/65402BFA JM38510/65402SEA M38510/65402BEA MM54HC259E/883
MM54HC259E/883C MM54HC259J MM54HC259J-MIL MM54HC259J/883
MM54HC259J/883B MM54HC259J/883C SN54HC259J SNJ54HC-259J
CD54HC259 8-Bit Addressable Latch Package Types
family combined
Ceramic Dual Inline Package (CDIP)

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