74FCT162511 Fast CMOS 16-Bit Registered - Latched Transceiver

The INTEGRATED DEVICE TECHNOLOGY (IDT) FCT162511T 16-bit registered/latched transceiver with parity is built using advanced dual metal CMOS technology. This high-speed, low-power transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The device has a parity generator/checker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. Separate error flags exits for each direction with a single error flag indicating an error for either byte in the A-to-B direction and a second error flag indicating an error for either byte in the B-to-A direction. The parity error flags are open drain outputs which can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. The parity error flags are enabled by the OExx control pins allowing the designer to disable the error flag during combinational transitions.

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74FCT162511NATPA	74FCT162511NBATPA	74FCT162511NBCTPA	74FCT162511NCTPA